High frame rate video signals are different from ordinary video signals. If analog signals are used for transmission, its analog bandwidth reaches several tens of megabytes or even one to two hundred megabytes, which makes it difficult to achieve long-distance transmission. The characteristics of large fiber transmission capacity, high quality and low interference are widely used in high-speed digital transmission systems. At present, there are quite a lot of fiber transmission systems for ordinary video signals at home and abroad, and there are few reports on non-standard high frame rate video signal fiber transmission systems, especially the realization of a single fiber transmission of two or more high frame rate video No report.
In this paper, two channels of 256 & TImes; 256 pixels and 1000 frames per second high-speed video signals need to be transmitted over a long distance. For high frame rate cameras, due to its high frame rate, the multi-channel parallel signal output method is usually used to reduce the data rate, and finally it is synthesized into a video signal by multiplexing. In order to achieve long-distance transmission, the paper proposes to use digital optical fiber multiplexing, demultiplexing and computer PCI technology to realize the transmission of 15MBps & TImes; 40 digital signals generated by two high frame rate video equipment and the synthesis of video signals and real-time computer display. 
1 System principle and structure
The optical fiber transmission system of high-speed video signal mainly includes multiplexing, optical transmission, optical receiving, demultiplexing, control circuit and PCI transmission interface. Figure 1 is a working principle diagram of the light emitting part of the system.
The 40 channels of 15MBps data obtained from high-speed video capture are first subjected to 2: 1 multiplexing in XC9572 to form 20 channels of 30MBps secondary multiplexed data to be provided to HDMP-1022, which completes the channel coding and converts it into a 600MBps PECL string Line data, drive the light emitting module to complete the fiber optic transmission of data. Figure 2 is a schematic diagram of the light receiving part.
The demultiplexing chip HDMP-1024 extracts 20 parallel data and a 30MHz clock signal from the 600MBpsPECL data received by the optical fiber receiving module, and then completes the second level demultiplexing by XC9572, and also PCI transmission composed of FIFO and PLX9052 The card provides timing signals, and the computer obtains real-time high-speed video acquisition data through the PCI bus, and displays and processes it.
2 Hardware design
The hardware design of the system mainly includes three parts: optical fiber transmission unit, PCI transmission unit and control unit. 
2.1 Design of digital optical fiber transmission unit
The digital optical fiber transmission unit mainly completes the multiplexing and demultiplexing functions of serial and parallel data. The design adopts the CIMT (CondiTIonal-Invert Master TransiTIon) channel coding method in data communication to encode the data. Figure 3 shows the format of the CIMT code.
CIMT codes have three frame forms: data frame, control frame and padding frame. The format of the data frame and control frame is shown in Figure 3 (a). Any data and control information that needs to be transmitted can be sent. Each frame starts with C-Field (Coding Field), followed by D-Field (Data Field ). Among them, the data bits composed of D-Field can be 16 bits or 20 bits. The system uses 20 bits of data; the control bit (C-Field) is composed of four data codes, and the receiving end can extract and lock the type of data. With status. Padding frames are generated when there is no data signal at the transmitter and when the transmitter and receiver establish a connection. At the main transient point of the three frames is the reference point for the recovered clock signal at the receiving end. In this system, Aglient's HDMP-1022 and HDMP-1024 are used as the main chips of the multiplexing and demultiplexing of CIMT code, and HFCT-5208 is used as the optical transmitter and receiver to realize the point-to-point optical fiber transmission design.
In the design of the optical transmitting end, the Double-Frame mode of HDMP-1022 is used to realize the transmission of 40 channels of data, and the capacity of its parallel data is expanded to 40 channels through two-stage multiplexing. Under the same clock control, the data is multiplexed into one high-speed signal at the same time, and another bit-inverted signal is generated at the same time, and finally the optical transmitter is pushed through the output of its CIMT encoder. Fig. 4 is a timing diagram of multiplexing transmission in a Double-Frame mode. Among them, CLOCK (15MHz) is a single-channel data acquisition clock, FLAG indicates the parity field, CAV and DAV indicate the control bits of the data frame and control frame, C0 ~ C39 indicate the input 40-channel signal, D0 ~ D19 are the DMT of CIMT code Data, STR-BOUT (30MHz) is the frequency-doubled clock after the chip is phase-locked.
At the optical receiving end, the optical receiver converts the obtained optical signal into a high-speed electrical signal and sends it to HDMP-1024. After demultiplexing, it extracts the reference clock signal STRBOUT (30MHz), data signals C0 ~ C39, and other states Control signal and data clock RCLK (15MHz). Figure 5 is a timing diagram of the Double-Frame optical receiver.
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2. 2 PCI transmission unit design
In order to achieve real-time recording of high-speed video signals, the PCI bus technology is used in the design. The PCI control chip uses PLX9052, which can be combined with FIFO to achieve a maximum data transfer rate of 120MBps digital input.
PLX9052 conforms to PCI 2.1 specification and supports low-cost slave adapters. It includes a 64-byte write FIFO and a 32-byte read FIFO. Through reading and writing FIFOs, high-performance burst data transmission can be achieved; its local bus and PCI bus clocks are independent of each other, and the local bus clock frequency The range is 0 ~ 40MHz, the clock frequency range of PCI is 0 ~ 33MHz; some important configuration information of PCI bus and local bus can be provided through serial EEPROM. PLX9052 supports burst memory mapping transmission and single-cycle memory or I / O mapping transmission, using 32-byte direct slave device read FIFO and 64-byte direct slave device write FIFO, mapped in PCI memory and I / O space The address in is set by the PCI base address register. Moreover, the local map register allows the PCI address space to be converted into a local address space. Figure 6 is a circuit diagram of the connection between PLX9052 and FIFO. IDT72205 from IDT is used for FIFO.
2. 3 control unit design
The timing control unit of the entire design is completed by CPLD. It mainly provides 2: 1 multiplexing of 40 signals, data latching and timing signals of system work at the optical transmitter; demultiplexing, FWO and PLX9052 provides corresponding sequential logic. This design selects Xilinx's XC9572 as the core chip of the control unit, and combines its online programming function to complete the timing debugging and design of the entire system.
Combining Verilog language and schematic (sch) method, the design of the whole system timing is well realized. The following is a 40-channel digital signal 8: 1 multiplexing Verilog language design code. 
3 Software design
The entire system software mainly includes the driver of the PCI transmission unit and the design of the system application program. PCI drivers under Windows include not only drivers for physical devices, but also virtual device drivers written for non-physical devices such as file systems. In the design, it is mainly designed for PCI driver under Windows2000. Because Windows 2000 prohibits user-mode programs from accessing I / O ports (Windows 95/98 allows user programs to directly access I / O ports), drivers that directly control physical devices are in kernel mode. The PCI driver of this design requires access to various hardware resources, so you should choose the zero-level driver mode.
The main development tool used for developing device drivers is the software package Windriver provided by JUNGO. This software package provides documentation for developing PLX9052 devices, header files and library files required for compilation, debugging tools and program examples. Use its internally defined low-level system services that can be called, such as DMA services, interrupt services, memory management services, installable file system services, etc., combined with VC ++ to complete the entire PCI device driver. This design includes the following aspects:
(1) PCI device initialization 
The PCI device driver first realizes the identification of the PLX9052 device, the addressing of the PLX9052 device's resources, and the service of interrupting the PLX9052 device. Mainly call the following functions in the Windirver software package:
WD_Open (hWD);
PCI_Get_WD_handle (& hWD);
PLX_LocateAndOpenBoard (0x10b5, 0x9052, UseInt);
(2) PCI port address operation
The PCI bus is a 32-bit bus standard. Double word (DWORD) operations are usually performed during I / O operations. Under Windows 2000, the system does not allow user programs and user mode drivers at priority 3 to use I directly. / O instruction. Any operation on I / O needs to be completed with the help of kernel mode driver. The author mainly calls two functions in the Windirver software package to complete. 
(3) Memory read and write
The data communication between PLX9052 and computer mainly adopts the DMA mode, and provides two functions of corresponding memory reading in Windriver. The data exchange between PLX9052 and computer memory can be realized by calling it.
The application development of the entire system is based on Microsoft's VC ++ development design, which can be used under the Windows 2000 operating system.
The entire optical fiber transmission system uses multiplexing and demultiplexing, combined with PCI technology to achieve long-distance transmission and control of high-speed video digital signals, real-time display and other functions. The transmission distance is 15km, and the recordable data volume is 128K bytes. At present, the design has been used in related test projects, and the capacity and stability of the expanded data will be further improved.
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