A multiplex section refers to a maintenance segment, including two regenerator section terminals (RSTs) and the fiber optic cable between them. It represents the path between the multiplex section termination functions in the Synchronous Digital Hierarchy (SDH) standard. The multiplex section function primarily involves sub-layer operations to implement protection at the multiplex section layer, making its implementation relatively complex. Network protection is a critical and essential function of SDH network elements, requiring detailed design. From an atomic model perspective, the multiplex section protection function divides the path termination function into sub-layer functions. This text describes a network element device with a four-fiber bidirectional multiplex section switching function, which is widely used in trunk networks, based on the device’s atomic function specifications. While the basic functions are still mainly reflected in the terminal and adaptation functions, the protection function is primarily embodied through the connection function.
SDH uses time-division multiplexing, where a signal representing "0 or 1" in one second becomes a signal that can represent N "0 or 1" levels in the same time. SDH typically operates at 14 Mbit/s, leading to STM-1, STM-4, STM-16, STM-64, and STM-128. Another concept involves multiplexing lower-speed signals such as 2M or 1.5M, 34M, and 45M into the basic STM-1 signal (e.g., 63 2M signals, 4 34M signals, or 3 45M signals).
How SDH Reuse Works
Although there are multiple routes for multiplexing a signal into an SDH STM-N signal, it is necessary to define a unique route for a country or region. China's optical synchronous transmission network technology system specifies the PDH series based on 2Mbit/s signals as the payload of SDH, selecting the AU-4 multiplexing route. The structure is illustrated in the figure below.
[Image: China's SDH Basic Multiplexing Mapping Structure]
1. Multiplexing 140Mbit/s into STM-N Signal
The C4 signal frame has 260 columns × 9 rows (when PDH signals are multiplexed into STM-N, the block frame remains at 9 lines). After adapting the E4 signal (C4 signal), the rate is calculated as follows: 8000 frames/second × 9 lines × 260 columns × 8 bits = 149.760 Mbit/s.
[Image: C4 Frame Structure Diagram]
The base frame of C4 (9 rows × 260 columns) is divided into 9 subframes, each containing 20 units (13-byte blocks). The first byte of each 13-byte block is W, X, Y, Y, Y, X, Y, Y, Y, X, Y, Y, Y, X, Y, Y, Y, X, Y, Z—totaling 20 bytes. The second to the 13th bytes contain 140Mbit/s information bits.
[Image: Subframe Structure of C-4]
Rate adaptation of the E4 signal is achieved by using the first byte of 180 13-byte blocks across 9 subframes. The C4 subframe equals 241W + 13Y + 5X + 1Z = 260 bytes = (1934I + S) + 5C + 130R + 10O = 2080 bits. Information bits I: 1934; fixed stuffing bits R: 130; overhead bits O: 10; adjustment control bits C: 5; adjustment opportunity bits S: 1.
To monitor the 140Mbit/s channel signal, a column overhead byte (high-order channel overhead VC4-POH) is added before the C4 block frame during multiplexing, forming the VC4 information structure.
[Image: VC4 Structure Diagram]
VC4 is the information payload of STM-1 frames. The PDH signal is packaged into C, and the corresponding channel overhead forms the VC information structure. This process is called mapping.
After packaging, the data can be loaded onto the STM-N. However, when the loading speed differs from the STM-N frame period (125 μs), the package may "float." To resolve this, SDH uses a management unit pointer (AU-PTR) in front of VC4, transforming the signal into the AU-4 information structure.
[Image: AU-4 Structure Diagram]
Although the package may float within the STM frame, the position of the AU-PTR is fixed because it resides in the segment overhead, allowing the receiving end to locate the AU-PTR and then find the VC4.
One or more AUGs...
Finally, adding the AU-4 to the SOH synthesizes the STM-1 signal, and N STM-1 signals are interleaved to form STM-N signals.
Second, 34Mbit/s is multiplexed into STM-N signal
The 34Mbit/s signal is adapted to the standard container C3 via rate adjustment, then packed with corresponding channel overhead to form VC3. The frame structure at this point is 9 rows × 85 columns. To facilitate locating VC3, a 3-byte pointer (TU-PTR) is added to the VC3 frame, creating the TU-3 information structure.
[Image: TU3 Structure Diagram after Loading TU-PTR]
The TU3 frame structure is modified by filling gaps to match the shown format.
[Image: TU3 Frame Structure Diagram after Filling the Gap]
In the figure, R represents pseudo-random information, and the structure is now TUG3 (branch unit group).
Three TUG3s are combined into a C4 signal structure via byte interleaving.
[Image: C4 Frame Structure Diagram]
At this stage, the remaining steps are C4 → VC4 → AU-4 → AUG → STM-N.
3. 2Mbit/s Multiplexing into STM-N Signal
First, the 2Mbit/s PDH signal is loaded into the standard container C12 via rate adaptation. A multiframe concept is used, combining four C12 base frames into one multiframe. The C12 base frame rate is 8000 frames/second, so the multiframe rate is 2000 frames/second.
[Image: C-12 Multiframe Structure and Byte Arrangement]
To monitor the performance of any 2Mbit/s channel signal in real-time, C12 is repackaged by adding corresponding channel overhead (low-order path overhead), forming the VC12 information structure. LP-POH (low-order path overhead) is added to the upper-left gap of each base frame. A multiframe includes 4 bytes of LP-POH: V5, J2, N2, K4. Each C12 multiframe carries 4 PCM30/32 frames, and the LP-POH monitors their transmission status.
To enable the receiver to correctly locate the VC12 frame, 4 bytes of TU-PTR are added to the 4 gaps of the VC12 multiframe, forming the TU12 information structure (9 rows × 4 columns). The TU-PTR indicates the starting point of the first VC12 in the multiframe.
Three TU12s are multiplexed into a TUG-2, forming a 9 rows × 12 columns frame.
Seven TUG-2s are multiplexed into a TUG-3. Note that the 7 TUG-2s form a 9 rows × 84 columns structure, requiring 2 columns of fixed stuffing bits to meet the TUG-3 requirement of 9 rows × 86 columns.
[Image: TUG3 Information Structure]
From the 2Mbit/s multiplexing process into STM-N signals, it can be seen that 3 TU12s make up one TUG2, 7 TUG2s make up one TUG3, 3 TUG3s make up one VC4, and one VC4 makes up one STM-1. Therefore, the 2Mbit/s multiplexing structure is a 3-7-3 configuration. Since the multiplexing method is byte interleaving, the arrangement of 63 VC12s in a VC4 is not sequential. The sequence number of the first TU12 differs from the next by 21.
There is a formula to calculate the TU12 serial number in different locations within the same VC4:
VC12 serial number = (TUG3 number + TUG2 number - 1) × 3 + (TU12 number - 1) × 21.
The location of the TU12 in the VC4 frame refers to two TU12s with the same TUG3 and TUG2 numbers but a TU12 number difference of 1. Here, the number refers to the position in the VC4 frame, with TUG3 ranging from 1–3, TUG2 from 1–7, and TU12 from 1–3. The TU12 serial number indicates the order of TU12s in the VC4 frame.
[Image: Emission Structure of TUG3, TUG2, and TU12 in VC4]
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