This scheme uses the combination of theoretical analysis and hardware circuit design to design the system and implement it with FPGA. System simulation and hardware circuit test results confirm the correctness of the design. The free oscillation frequency of the phase-locked loop can be changed with the change of the input signal frequency, and has the characteristics of simple circuit structure, wide phase locking range, fast locking speed and small steady-state error.
0 Preface
The phase-locked loop is a closed-loop automatic control system whose output signal can track the phase of the input signal. Due to its unique excellent performance, it is widely used in communication, radar, measurement and automation control.
Compared with the analog phase-locked loop, the all-digital phase-locked loop (ADPLL) has the characteristics of high reliability, stable parameters and easy integration. It has been studied more and more extensively and has become an indispensable component in various electronic devices.
The phase-locked loop has three important performance metrics: phase-locked range, phase-locked speed, and stability. In order to improve the performance indicators of phase-locked loops, some scholars have conducted in-depth analysis and research.
In this paper, a composite control method based on adaptive proportional integral is proposed to overcome the problem of phase-locking range, phase-locked speed and stability between phase-locked loops.
1 The structure and working principle of the all-digital phase-locked loop
The system consists of four modules: digital phase detector, adaptive controller, digital filter and numerically controlled oscillator, as shown in Figure 1. The working principle of each module is described in detail below.
The ADPLL uses a dual D-trigger digital phase detector. The phase detector compares the phases of the input signal and the output signal, and outputs a signal sub(add) whose reaction phase leads (or lags). Sub and add not only reflect the lead lag of the phase, but also reflect the phase error. size. Its structural block diagram is shown in Figure 2.
The adaptive controller module mainly plays a role in adjusting the loop bandwidth. On one hand, the controller discriminates the input signal, on the other hand, quantizes the phase error signal sub, add, and calculates the filter control parameter M according to the quantized value. If the input signal frequency changes greatly, the controller issues control. The signal sig, the control parameter M is assigned to the filter, and the periodic reset invertible counter and the non-reset invertible counter are initially set, thereby rapidly adjusting the frequency capture and the loop bandwidth.
The loop filter is mainly composed of a periodic reset invertible counter and a non-reset invertible counter, wherein the system high frequency clock clk is its synchronous clock signal, and add and sub are used as the up and down count enable control signals of the two counters. When the count enable signal is high, the two counters perform corresponding 1 plus or minus 1 operations when the rising edge of the clk clock arrives. When the count enable is low, the count value remains unchanged. When the rising edge of the input signal fin comes, the count values ​​of the two counters are shifted and added, and the addition result is sent to the latch as the control parameter N of the numerically controlled oscillator, and then the proportional counter is reset.
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