**Introduction**
Portable power supply design requires a comprehensive system-level approach. When developing battery-powered devices such as smartphones, MP3 players, PDAs, PMPs, and digital still cameras, the power system design plays a crucial role in determining the overall performance and efficiency of the device. A well-designed power architecture ensures optimal energy utilization, component selection, software integration, and efficient power distribution. In addition, from a system design perspective, it is essential to prioritize energy conservation to extend battery life and improve user experience. One effective solution for this is the use of a low dropout linear regulator (LDO) with enable control, which offers flexibility and efficiency in managing power consumption.
**Power Requirements for RF Circuits**
Most baseband chipsets in cellular phones require three distinct power supplies to support digital, analog, and peripheral interface circuits. The digital circuitry typically operates at 1.8V to 2.6V, while the battery voltage drops to around 3.2V–3.3V when the device is turned off. An LDO with a dropout voltage of at least 500–600mV can efficiently handle this range. Since digital circuits do not demand high PSRR or low noise, they primarily require minimal quiescent current under light loads.
The analog section of the baseband processor usually needs a supply voltage between 2.4V and 3.0V, with a dropout voltage of 200–600mV. In this case, the LDO must provide high ripple rejection, especially at low frequencies like 217 Hz in GSM phones, to eliminate noise generated by RF power amplifiers. Additionally, the LDO should maintain low quiescent current to preserve battery life.
For RF circuits, including low-noise amplifiers (LNAs), mixers, phase-locked loops (PLLs), and voltage-controlled oscillators (VCOs), the supply voltage is typically 2.6V–3.0V. These components are highly sensitive to noise, so a low-noise, high-PSRR LDO is essential. The performance of VCO and PLL circuits directly impacts RF specifications such as signal purity, receiver selectivity, and phase error. Any noise introduced into these circuits can affect oscillator stability and potentially modulate the carrier signal.
**LDO Noise and Power Supply Rejection Ratio (PSRR)**
An LDO is a micropower, low-dropout linear regulator known for its low self-noise and high PSRR. Its block diagram is shown in Figure 1. The PSRR is an AC parameter that measures how well the LDO suppresses input voltage ripples on the output. Unlike noise, which is generally in the 10Hz–100kHz range, PSRR is evaluated across a wide frequency spectrum. The formula for PSRR in decibels is:
**PSRR = 20log(ΔVin / ΔVout)**
Figure 2 illustrates the input and output voltage changes of the SGM2007 at CBP = 0.01mF, ILOAD = 50mA, COUT = 1mF, and f = 10kHz. From the equation, if the input changes by 1V and the output changes by 1mV, the PSRR is 60dB, indicating strong ripple suppression capability.
The output noise of an LDO is influenced by internal design and external bypass and compensation circuits. As shown in Figure 1, the reference source is the main contributor to output noise. The noise from the reference is amplified at the output, and the formula for output noise is:
**Vn = (R1 + R2)/R2 × Vref**
The reference bypass capacitor (CBP) can significantly reduce reference noise. Ceramic capacitors are commonly used, with typical values ranging from 470pF to 0.01mF. However, larger capacitors may slow down the output voltage rise time, so careful selection is necessary.
Other factors affecting output noise include internal poles, zeros, and load conditions. Increasing the output capacitance or reducing the load can help lower high-frequency noise. Figures 3 and 4 show how the reference bypass capacitor affects both noise and PSRR in the SGM2007. It's clear that increasing CBP improves PSRR at certain frequencies.
LDOs also require external input and output capacitors. Large-capacity capacitors with low ESR enhance overall PSRR, noise performance, and transient response. Ceramic capacitors are preferred due to their low cost and failure mode (open circuit), unlike tantalum capacitors, which may short-circuit. The ESR of the output capacitor influences stability, and ceramic capacitors typically have ESR values in the range of 10mΩ. X5R and X7R dielectric materials are recommended for better temperature stability.
Figures 5 and 6 demonstrate the effect of output capacitance (Cout) on the noise and PSRR of the SGM2007. Larger capacitors generally result in reduced output noise and improved PSRR over a wide frequency range. This makes them a critical consideration in RF applications where signal integrity is paramount.
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