PIC microcontroller learning notes

Single chip microcomputer STM32L151CCU6

1206RGB (single)

GW MB10F 0.8A 1000V rectifier bridge

RF cable can be customized for other specifications

0201 package SLP0603 ESD electrostatic diode 5V one-way ESD

1. Status register STATUS

2. Indirect addressing registers INDF and FSR
3. Register PCL and PCLATH related to the program counter PC
4. Power Control Register PCON

PIC microcontroller instruction system
The PIC16F87X has a total of 35 instructions, each of which is a 14-bit single-byte instruction. All instructions are divided into three categories based on the operation object: byte-oriented operations (17), bit-oriented operations (4), and constant or control operations (14). PIC configuration word settings
There are two common methods for configuring the PIC configuration word:
1. Using two underscores followed by CONFIG and then the value after setting the configuration word.
2. Using two underscores followed by CONFIG, and then specifying the bits and status of each configuration word. The format is as follows:
;========================================================== =================
; Configuration word definition
;========================================================== =================
__CONFIG _DEBUG_OFF&_CP_ALL&_CPD_ON&_LVP_OFF&_BODEN_OFF&_PWRTE_ON&_WDT_OFF&_HS_OSC ; Configuration Word Definition
Indirect Addressing, INDF and FSR Registers
The INDF register is not a physical register. Accessing it results in indirect addressing. Indirect addressing uses the INDF register, where any instruction targeting INDF actually accesses the register pointed to by the FSR pointer. Reading from INDF itself returns 00H. Writing to INDF through indirect addressing performs a dummy operation (though it may affect status bits). A valid 9-bit address is formed by combining the 8-bit FSR register with the IRP bit (from STATUS). Example of indirect addressing:
Example: Write values from 30H to 7FH sequentially. COUNT is the counter register.
;========================================================== ================
; Continuous address write data subroutine (indirect addressing)
;========================================================== ================
WR_ADS: MOVLW 30H; initialize RAM contents
MOVWF FSR; start at 30H
MOVLW 30H; assign 30H to 30H unit
MOVWF COUNT;
INTRAM: MOVF COUNT, 0; assign 30H to 7FH
MOVWF INDF; access INDF
INCF COUNT, 1; increment COUNT
INCF FSR, 1; move pointer
BTFSS COUNT, 7; check if COUNT is 1 (COUNT=0 at 7FH)
GOTO INTRAM; loop
RETURN; return from subroutine In PIC microcontroller programming, you need to define the registers you use. Typically, pseudo-instructions are used. However, using the CBLOCK directive makes it easier. Define multiple registers together, and the addresses will be automatically assigned. End the block with ENDC.
Example:
;========================================================== ================
; Space definition
;========================================================== ================
CBLOCK 20H; start at 20H
COUNT; address 20H
W_TEMP; address 21H
STATUS_W; address 22H
ENDC; end definition I/O operations on PIC microcontrollers involve setting a bit in the TRISX register to put the corresponding output driver in high-impedance mode. Clearing a bit in TRISX latches the output latch to the specified pin. RCSTA Register Operation Notes
When receiving data, if the received data is read promptly, the USART will normally receive the next data. However, if an interrupt occurs during reception, or another operation interrupts it, the data in RCREG may be delayed. This causes the shift register to stop sending data to RCREG. As a result, even if more data is sent, the RCIF flag won’t set, and the reception stops. If no action is taken, communication fails. The cause is that the interruption delays reading the data, triggering the OERR flag in RCSTA. This flag disables the shift register from placing new data into RCREG. To fix this, clear OERR by first clearing the CREN bit (RCSTA), then re-enabling it. Otherwise, only one byte can be received.