Someone on the STMCU community website asked the following question:
"I am using two DMAs of the STM32F407, both triggered by a timer. However, I found that DMA1 is unable to transfer the IDR data from GPIO to memory. During debugging, the DMA1 data stream transmission error flag is set, but there’s no issue when using DMA2. Additionally, when I changed the GPIO's IDR to the TIM5 ARR under APB1, DMA1 worked properly. Can you explain why this happens?"
The consultant mentioned DMA1 and DMA2 in the STM32F4 series, along with peripherals like GPIO and TIM5. To better understand this issue, it's important to look at the bus architecture of the STM32F407. The system consists of multiple layers of 32-bit AHB bus matrices and master-slave buses, enabling efficient access between different modules. It's worth noting that the 64KB CCM in the STM32F4 series does not go through the bus matrix and can only be accessed by the CPU—DMA cannot access it directly.
Let’s take a closer look at the bus access diagrams for DMA1 and DMA2 on the STM32F407. Both DMAs have dual AHB bus access ports—one for memory and one for peripheral access.
When combining this diagram with the overall system memory bus structure, it becomes clear that the peripheral access ports of DMA1 and DMA2 are connected differently. The DMA2 peripheral port is connected to the bus matrix, allowing it to access AHB peripherals via the matrix and then connect to the AHB-APB bridge 2 to reach APB2 peripherals. In contrast, DMA1 is not connected to the bus matrix and only connects to AHB-APB bridge 1, which allows it to access APB1 peripherals.
Now, the problem is that DMA1 cannot access GPIO but works with TIM5. Looking at the device overview in the datasheet, we can see how the peripherals are connected. The GPIO peripheral is connected to AHB1, while TIM5 is connected to APB1. From the DMA access block diagram, it’s clear that the DMA1 peripheral port is not connected to AHB1 at all, so it can't access GPIO. However, DMA2 can because it goes through the bus matrix and accesses AHB1 peripherals.
As for why DMA1 can access TIM5, it's because its AHB peripheral port passes through the AHB/APB1 bridge, allowing it to access any APB1 peripherals—including TIM5.
In summary, the answer to the user’s question lies in understanding the differences in bus connections between DMA1 and DMA2. These diagrams are essential for troubleshooting and understanding the limitations of each DMA channel. They visually clarify complex interactions between peripherals and the system bus, making them invaluable for developers working with STM32 microcontrollers. Always pay attention to these technical illustrations—they often contain crucial information that can save time and prevent errors.
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